Semiconductor devices can include electrically erasable and electrically programmable read only memory cells. One of the problems in using these devices has traditionally been having to incorporate relatively high potentials for programming or erasing the memory cells. As the potentials being supplied to the device are reduced, keeping the same thick dielectric layers for both a select transistor and a floating gate transistor become more difficult as this greatly impairs reading and writing times.
An attempt to address part of the high potential problems has been the use of a uniformly thick tunnel dielectric layer under both the select transistor and storage transistor. Referring to FIG. 1, a P-well 10 includes N+ doped regions 12,14, and 16 that are the source, drain/source and drain regions, respectively, for the memory cell 11. The memory cell 11 includes a storage transistor 29 and a select transistor 28. The storage transistor 29 has a floating gate 22, a control gate 26, and an intergate dielectric layer 24 between the floating gate 22 and the control gate 26. The select transistor 28 has a select gate 20. The storage transistor 29 is where charge is stored for the memory cell and it is connected to the drain of the memory device. A tunnel dielectric layer 18 lies between the P-well 10 and the select and floating gates 20 and 22.
This particular device has been found to be susceptible to drain disturb problems during programming. The potentials for programming, erasing and reading this device are shown in FIG. 2. The drain region 16 is typically at a potential of approximately 6 volts during programming of the memory cell 11 and supplies about half the potential necessary for electron transport from the floating gate to the drain. However, this potential can disturb the data in other memory cells that are connected to the same drain bit line. More specifically, the unselected memory cells along the same column will have their control gates at approximately zero volts while the drain regions are at potentials of approximately 6 volts. Some electrons are ejected from floating gates that share the same bit line of other memory cells to their drains.
The drain disturb can be particularly problematic as implemented into an electrically erasable programmable read only memory (EEPROM) that is bit erasable or byte erasable. In these particular types of memory, the data in other cells can change relatively frequently while the data in one memory cell is not intentionally changed. However, the frequent programming of other memory cells sharing the same drain bit line can change an unselected bit from an unprogrammed state to a programmed state. This unintentional programming affects the reliability of the device.
Some prior art references include layouts where the select gate transistor is at the drain side of the memory cell and the dielectric layer for the select transistor is typically very thick. The thick dielectric is necessary because a very high potential is used on the select gate during programming to transmit the high drain voltage to the drain of the storage transistor. However, the thick gate dielectric layer causes the access time of the memory cell to be relatively long.